Non-volatile memory devices are commonly used in many different types of electronic systems (e.g., computers, mobile phones, PDAs, etc.) that require the storage of binary data or bits of information that are to be maintained even when the memory devices are not powered.
For example, electrically erasable and programmable non-volatile memory devices, also identified by the acronym EEPROM (Electrically Erasable Programmable Read Only Memory), have reached a widespread use in the electronic applications market, from an industrial level to the consumer level. Such wide distribution is due to special features, such as the ability to maintain information without power being supplied, to allow the editing of information itself, and to ensure greater reliability and robustness than other memory devices, such as magnetic-disk memory devices.
Flash memory devices are currently the most commonly used type of EEPROM devices since, besides the above mentioned features, they have a very high storage capacity and are at the same time very small. In general, each flash memory device includes a plurality of sectors of memory cells electrically erasable and programmable. Each sector is formed in a respective electrically isolated well of the chip. Each memory cell typically includes an n-channel MOS transistor with a floating gate structure. Such a transistor has a collection electrode (drain), a source electrode (source) and a control electrode (gate) in a completely similar way as a standard MOS transistor, but with the addition of a further floating control electrode (floating gate) that is buried in an oxide layer that is to be electrically isolated.
The information bit is physically stored in each memory cell in the form of an electric charge in the floating gate, which defines a corresponding threshold voltage of the transistor. In particular, the memory cell is erased to a low threshold voltage (floating gate essentially free from electrical charges), for example, equivalent to a high logic value, and programmed to a high threshold voltage (electrical charges trapped in the floating gate), for example, equivalent to a low logic value. In flash memory devices the programming may be performed on memory cells individually selected, while the erasing may be performed on entire selected sectors (even simultaneously on multiple of them). Each memory cell has to absorb certain amounts of electrical power for being successfully programmed or erased.
The current trend of electronic systems development is towards an ever greater data processing speed, and involves the need to develop non-volatile memory devices that can read/program bits faster and faster, mainly through parallel access to an ever-larger amount of memory cells. At the same time, a tendency has developed to reduce the operating voltages (scaling) of electronic devices. This is to reduce electrical power consumptions, which ensures a greater autonomy to battery-powered portable electronic systems. These devices currently occupy an increasing share of the market by way of the electronic products in which they are implemented.
Unfortunately, the increased speed and reduced power consumption are parameters in conflict with one another. The maximum electrical power available during each programming operation defines the maximum amount of memory cells that may simultaneously undergo the programming operation. In other words, the maximum available electrical power imposes a limit on the number of parallel programmable cells, and then, also on the programming speed of the memory device.
The approaches currently developed seem to prefer a tradeoff between the speed and power consumption of the memory devices. For example, in the first case, devices are provided with a dedicated power circuit (e.g., charge pump voltage multiplier circuits) to provide greater electrical power to allow simultaneous programming of an increased number of memory cells. However, applying such an approach results in the area of the memory device and its power consumption being increased, which increases both production costs and operating costs thereof.
Another more popular approach involves splitting a word of binary data, which is used for data processing in the electronic system in which the memory device is implemented, into segments according to the number of parallel programmable cells. The splitting is performed by an appropriate filter circuitry that divides the word of binary data in segments. The segments have a bit length corresponding to the number of memory cells that may be parallel programmed. This is defined by the maximum electrical power available for each programming operation.
The programming operation of the whole word is then divided into a number of subsequent programming cycles equal to the number of segments in which the word was divided. In particular, during each programming cycle the bits at a low logic value included in the segment are identified and programmed in the corresponding memory cells. This approach allows management of the programming of bit words having a large size.
However, the programming operation of the whole word requires multiple cycles, thus requiring a programming time that is often considerable, and which increases with the word length. For example, a memory device may be able to parallel program 16 memory cells, while the electronic system in which it is implemented operates with 64-bit words. In these conditions, the filter circuitry divides each word into four segments of 16 bits each, which is to be analyzed and programmed in four consecutive programming cycles. Consequently, the memory device will be occupied for four consecutive cycles for each word being programmed.